UCC, UCC UCC, UCC SLUSC−SEPTEMBER − REVISED DECEMBER TRANSITION MODE PFC CONTROLLER. 1 . UCCP IC PFC CTLR TRANS-MODE 8-DIP Texas Instruments datasheet pdf data sheet FREE from Datasheet (data sheet) search for. Details, datasheet, quote on part number: UCC Part family, UCC PFC Controller for low to medium power applications requiring compliance with.

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It is designed for controlling a boost preregulator operating in transition mode also referred to as boundary conduction mode or critical conduction mode operation. It features a transconductance voltage amplifier for feedback error processing, a simple multiplier for generating a current dataaheet proportional to the input voltage, a current-sense PWM comparator, PWM logic and a totem-pole driver for driving an external FET.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Additionally, the controller provides features such as peak current limit, default timer, overvoltage protection OVP and enable. The UCC and UCC, while being pin compatible with other industry controllers providing similar functionality, eatasheet many feature enhancements and tighter specifications, leading to an overall reduction in system implementation cost.

The system performance is enhanced datasyeet incorporation of zero power detect function which allows the controller output to shut down at light load conditions without running into overvoltage. The device also features innovative slew rate enhancement circuits which improve the large signal transient performance of the voltage error amplifier.

Datasehet low start-up and operating currents of the device results in low power consumption and ease of start-up. Highly accurate internal bandgap reference leads to tight regulation of output voltage in normal and OVP conditions, resulting in higher system reliability.

Texas Instruments

The enable comparator ensures that the controller is off if the feedback sense path is broken or if the input voltage is very low. The UCC gM amplifier also provides a full 1. The UCC is suitable for multiple applications including AC adapters where a two-stage power conversion is needed. The UCC is suitable for applications such as electronic ballasts where there is no down-stream PWM conversion and the advantages of smaller VCC capacitor and improved transient response can be realized.

Add R suffix to device type e. UCCDR to order quantities of 2, devices per reel. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. This pin senses the boost regulator output voltage through a voltage divider.

Internally, this pin is the inverting input to the transconductance amplifier with a nominal value of 2. Additionally, pulling this pin below the ENABLE threshold turns off the output switching, ensuring that the gate drive is held off while the boost output is pre-charging and also ensuring no runaway if feedback path is open. Output of the transconductance error amplifier. Loop compensation components are connected between this pin and ground. This voltage is one of the inputs to the multiplier, with a dynamic input range of 2.

During zero power or overvoltage conditions, this pin goes below 2. When it goes below 2. This pin senses the instantaneous boost regulator input voltage through a voltage divider.

The voltage acts as one of the inputs to the internal multiplier. Recommended operating range is 0 V to 2. This pin senses the instantaneous switch current in the boost switch and uses it as the internal ramp for PWM comparator. The internal circuitry filters out switching noise spikes without requiring external components.


In addition, an external R-C filter may be required to suppress the noise spikes. An internal clamp on the multiplier output terminates the switching cycle if this pin voltage exceeds 1.

Additional external filtering may be required. CS threshold is approximately equal to: This pin is the input for the zero current detect comparator. The boost inductor current is indirectly sensed through the bias winding on the boost inductor. The ZCD pin input goes low when the inductor current reaches zero and that transition is detected. Internal active voltage clamps are provided to prevent this pin from going below ground or too high. The chip reference ground. All bypassing elements are connected to ground pin with shortest loops feasible.

The gate drive output for an external boost switch. This output is capable of delivering up to mA peak currents during turn-on and turn-off. An external gate drive resistor may be needed to limit the peak current depending on the VCC voltage being used. Below the UVLO threshold, the output is held low. The supply voltage for the chip. This pin should be bypassed with a high-frequency capacitor greater than 0. In addition to generating a 2. An internal rail of 7. The advantage in using a transconductance amplifier is that the inverting input of the amplifier is solely determined by the external resistive-divider from the output voltage and not the transient behavior of the amplifier itself.

Enhanced slew-rate of the compensation capacitor results in a faster start-up and transient response. The limited source current in the UCC helps to gradually increase the error voltage on the COMP pin preventing a step increase in line current. This is indirectly sensed with a secondary winding that is connected to the ZCD pin. The internal active clamp circuitry prevents the voltage from going to a negative or a high positive value.

Texas Instruments – datasheet pdf

The clamp has the sink and source capability of 10 mA. The resistor datassheet in series with the secondary winding should be chosen to limit the ZCD current to less than 10 mA.

The rising edge threshold of the ZCD comparator can be as satasheet as 2. This translates to a minimum datasheey frequency of 5 kHz. In other words, the boost inductor value should be chosen for switching frequencies greater than 5 kHz. The slew rate enhancement circuitry of the gM amplifier that is activated during overvoltage conditions slews the COMP pin to about 2. This ensures that the zero power comparator is not activated during transient behavior when the slew rate enhancement circuitry is enhanced.

Multiplier Block The multiplier block has two inputs. The multiplier output is approximately 0. The dynamic range of the inputs can be found in the electrical characteristics table. Overvoltage Protection OVP Block The OVP feature in the part is not activated under most operating conditions because of the presence of the slew rate enhancement circuitry present in the error amplifier. This prevents further rise in output voltage. This prevents satasheet output dc voltage from going above 7.

Transition Mode Control The boost converter, the most common topology used for power factor correction, can operate in two modes — continuous conduction code CCM and discontinuous conduction mode DCM.

Transition mode control, also referred to as daatasheet conduction mode CRM or boundary conduction mode, maintains the converter at the boundary between CCM and DCM by adjusting the switching frequency. The CRM converter typically uses a variation of hysteretic control with the lower boundary equal to zero current.


It is a variable frequency control technique that has inherently stable input current control while eliminating reverse recovery rectifier datasehet.

As shown in Figure 1, the switch current is compared to the reference signal output of the multiplier directly.

This control method has the advantage of simple implementation and still can provide very good power factor correction. However, implementations of the control functions are different. The current profile is also different and affects the component power loss datwsheet filtering requirements.

The filtering requirement is not severe and therefore is not a disadvantage. For medium to higher power applications, where the input filter requirements dominate the size of the magnetics, the CCM boost is 28501 better choice due to lower peak currents which reduces conduction losses and lower ripple current which reduces filter requirements.

The main tradeoff in using CRM boost is lower losses due to no reverse recovery in the boost diode vs. Design Procedure For a selected VOUT and minimum switching frequency, the following equations outline the design guidelines for power stage 82051 selection. Refer to the typical application diagram for reference designators. Inductor Selection In the transition mode control, the inductor value needs to be calculated to start the next switching cycle at zero current.

It is important to choose datahseet device that minimizes gate charge and capacitance and minimizes the sum of datasyeet and conduction losses at a given frequency. The diode selection is based on reverse voltage, forward current, and switching speed. ESR and the maximum RMS ripple current rating may also be important especially at higher power levels.

Select the value of CAC1 so that the corner frequency of the resulting filter is greater than the lowest switching frequency. Keep in mind that the low corner frequency of this filter may compromise the overall power factor. The value of RS1 is thus selected for maximum power operation at low ac line voltage conditions. RS2 and RS3 can be added for further scaling.

IC datasheet pdf-ucc,pdf datasheet (TRANSITION MODE PFC CONTROLLER)_百度文库

The CS pin already has an internal filter for noise due to switching transients. Additional filtering at switching transient frequencies can be achieved by adding CS1.

Voltage Loop Design How well the voltage control loop datasneet designed directly impacts line current distortion. UCC employs a transconductance amplifier gM amp with gain scheduling for improved transient response refer to Figure Integral type control at low frequencies is xatasheet here because the loop gain varies considerably with line conditions.

The largest gain occurs at maximum line voltage. If the power factor corrector load is dc-to-dc switching converter, the small signal model of the controller and the power factor corrector, from COMP to PFC datasgeet voltage is given by: The resulting gM amplifer configuration is shown in Figure 3. The crossover frequency of the control loop will be much lower than twice the ac line voltage. In order to choose the compensator dynamics, determine the maximum allowable loop gain at twice the line frequency and solve for capacitor CV2.